In the technology for manufacturing an integrated circuit, for example, a MOS transistor, a gate structure including an insulating layer with high dielectric constant (high-K) and a metal gate (hereafter called HK/MG for short) has been widely developed and used. Currently, the HK/MG can be fabricated by either a gate-last process or a gate-first process. For example, in the gate-last process, a chemical mechanical polish (CMP) is generally applied onto an interlevel dielectric (ILD) layer covering the poly-silicon dummy gate so as to expose the poly-silicon dummy gate, which is also called as a poly opening polish process. After the poly opening polish process, the poly-silicon dummy gate is removed and the metal gate of the HK/MG is filled to replace the poly-silicon dummy gate.
However, typically, in the poly opening polish process, an abrasive (e.g., a colloid silica) of a polishing slurry in the chemical mechanical polish is prone to form an oxide residue (e.g., a silicon oxide) deposited on the exposed poly-silicon dummy gate. Furthermore, the oxide residue can not be effectively removed in the subsequent steps of the typical poly opening polish process such as a water cleaning step and a post cleaning step. The oxide residue deposited on the exposed poly-silicon dummy gate will affect removing the poly-silicon dummy gate and the deposition of the metal gate, thereby affecting the performance of the integrated circuit. On the other hand, the deposited oxide residue will decrease the life time of a polishing pad, thereby increasing the production cost of the integrated circuit.
Therefore, what is needed is a poly opening polish process to overcome the above disadvantages.